For a typical computer system to transfer data to a network, the data is packaged as messages and transferred to the network through an input/output (I/O) channel. The I/O channel is typically in the form of an I/O board. As messages are transferred from the computer processor to the I/O board, the messages wait in the I/O board until the network is ready to act on these messages. Thus, the I/O board includes a buffer memory to hold these messages before they are transmitted to the network.
Messages are typically stored in the buffer memory using a First-In-First-Out (FIFO) Queue data structure. Messages are received into this FIFO Queue from the computer system. Messages are removed from this FIFO Queue for transmission to the network.
Prior art computer processors transmit messages to the I/O board when the I/O board has room to accept these messages. If the buffer memory within the I/O board becomes completely filled, then the computer processor simply stops sending messages to the I/O board. The I/O board then continues to transmit messages to the network as quickly as the network accepts these messages. When the buffer memory within the I/O board achieves a certain level of memory availability, the computer processor resumes sending messages to the I/O board.
In effect, using this scheme, the buffer memory within the I/O board becomes flooded with messages. When the buffer memory within the I/O board reaches a certain level of memory availability, "flooding" of the I/O board resumes. Thus, the buffer memory within the I/O board experiences large transitions in its memory utilization.
There are numerous disadvantages in such erratic use of an I/O board. The I/O channel is being used inefficiently because the channel is varying with either extremely high traffic usage or no traffic usage. Furthermore, because the amount of message transmissions are not being accomplished at a smooth level, system performance is degraded. In addition, the need to constantly start and stop message transmission to the I/O board results in an increase to computer processor overhead. All of these attributes are undesirable with regard overall processor utilization.